74ALVCH16821: 20-bit bus-interface D-type flip-flop' positive-edge trigger (3-State) (Based on PIP 74ALVCH16821)

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

74ALVCH16821: Product Block Diagram
Outline 3d SOT371-1
Data Sheets (1)
Name/DescriptionModified Date
20-bit bus-interface D-type flip-flop' positive-edge trigger (3-state) (REV 2.0) PDF (95.0 kB) 74ALVCH16821 [English]14 Mar 2014
Application Notes (5)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
Brochures (3)
Name/DescriptionModified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (2)
Name/DescriptionModified Date
plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English]08 Feb 2016
plastic shrink small outline package; 56 leads; body width 7.5 mm (REV 1.0) PDF (530.0 kB) SOT371-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English]15 Apr 2013
Supporting Information (2)
Name/DescriptionModified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS Model
Ordering Information
ProductStatus
74ALVCH16821DGGActive
74ALVCH16821DLActive
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74ALVCH16821DLSOT371-1SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
Tube in DrypackActive74ALVCH16821DL,512 (9352 590 00512)ALVCH1682174ALVCH16821DLweek 13, 2005123.83.872.58E812
Reel 13" Q1/T1 in DrypackActive74ALVCH16821DL,518 (9352 590 00518)ALVCH1682174ALVCH16821DLweek 13, 2005123.83.872.58E812
Reel 13" Q1/T1Withdrawn74ALVCH16821DL,118 (9352 590 00118)ALVCH1682174ALVCH16821DLAlways Pb-free123.83.872.58E811
74ALVCH16821DGGSOT364-1SSOP-TSSOP-VSO-WAVETube in DrypackActive74ALVCH16821DGGS (9352 590 10512)ALVCH1682174ALVCH16821DGGAlways Pb-free123.83.872.58E811
Reel 13" Q1/T1 in DrypackActive74ALVCH16821DGGY (9352 590 10518)ALVCH1682174ALVCH16821DGGAlways Pb-free123.83.872.58E811
Bulk PackDiscontinued74ALVCH16821DGG:11 (9352 590 10112)ALVCH1682174ALVCH16821DGGweek 2, 2006123.83.872.58E811
Reel 13" Q1/T1Discontinued74ALVCH16821DGG,11 (9352 590 10118)ALVCH1682174ALVCH16821DGGweek 2, 2006123.83.872.58E811
20-bit bus-interface D-type flip-flop' positive-edge trigger (3-state) 74ALVCH16821DL
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
Low voltage CMOS family - LVC 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
alvch16821 IBIS model 74ALVCH16821DL
SOT371-1 74LVT16543ADL
Footprint for reflow soldering 74HC_T_595_Q100
plastic thin shrink small outline package; 56 leads; body width 6.1 mm pcf8576d_automotive
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... pcf8576d_automotive
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