74AUP1G04GW: Low-power inverter

The 74AUP1G04 provides the single inverting buffer.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP1G04GW: Product Block Diagram
Outline 3d SOT353-1
Data Sheets (1)
Name/DescriptionModified Date
Low-power inverter (REV 7.0) PDF (416.0 kB) 74AUP1G04 [English]27 Jun 2012
Application Notes (3)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic thin shrink small outline package; 5 leads; body width 1.25 mm (REV 1.0) PDF (223.0 kB) SOT353-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... (REV 1.0) PDF (257.0 kB) SOT353-1_125 [English]15 May 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT353 Topmark (REV 1.0) PDF (103.0 kB) MAR_SOT353 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionOutput drive capability (mA)Package versionfmax (MHz)No of bitstpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1G04GWActiveAUPBuffers/inverters/drivers1.1 - 3.6CMOSsingle inverter+/- 1.9SOT353-17014ultra low-40~12530979.2179TSSOP55
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74AUP1G04GWSOT353-1Reel 7" Q3/T4, ReverseActive74AUP1G04GW,125 (9352 790 03125)pC74AUP1G04GWAlways Pb-free0.03.293.04E811
Low-power inverter 74AUP1G04GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT353 Topmark 74LVC1G17_Q100
74AUP1G04 IBIS model 74AUP1G04GW
plastic thin shrink small outline package; 5 leads; body width 1.25 mm 74LVC1G17_Q100
TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... 74LVC1G17_Q100
74AUP3G04
XC7SH14