74AUP1G0832GS: Low-power 3-input AND-OR gate _ BDTIC a Leading Distributor in China

74AUP1G0832GS: Low-power 3-input AND-OR gate

The 74AUP1G0832 provides the Boolean function: Y = (A × B) + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP1G0832GS: Product Block Diagram

sot1202_3d

Data Sheets (1)

Name/Description	Modified Date
Low-power 3-input AND-OR gate (REV 5.0) PDF (260.0 kB) 74AUP1G0832 [English]	22 Jun 2012

Application Notes (2)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]	06 May 2011

Brochures (3)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm (REV 1.0) PDF (192.0 kB) SOT1202 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1202_132 [English]	04 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
MAR_SOT1202 Topmark (REV 1.0) PDF (49.0 kB) MAR_SOT1202 [English]	03 Jun 2013

IBIS Model

aup1g0832 IBIS model (REV 2.0) ibs AUP1G0832 12/22/2014
74AUP1G08 IBIS model (REV 1.0) ibs AUP1G08 12/15/2014

Ordering Information

Product	Status	Family	Function	V_CC (V)	Type	Logic switching levels	Description	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP1G0832GS	Active	AUP	Combination	1.1 - 3.6	Combination gates	CMOS	single 3-input AND-OR gate	+/- 1.9	SOT1202	6.7	70	1	ultra low	-40~125	272	14.8	177	XSON6	6

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	MSL	MSL LF
74AUP1G0832GS		SOT1202		Reel 7" Q1/T1, Q3/T4	Active	74AUP1G0832GS,132 (9352 928 32132)	aY	74AUP1G0832GS		Always Pb-free	1	1

Low-power 3-input AND-OR gate 74AUP1G0832GS

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

Pin FMEA for AUP family 74AUP1T34GW-Q100

電圧レベルシフタ 74AVC16245DGG-Q100

NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100

Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100

ロジック製品セレクションガイド... 74LVC_H_245A_Q100

Logic selection guide 2016 74LVC_H_245A_Q100

MAR_SOT1202 Topmark NCX2200GS

aup1g0832 IBIS model 74AUP1G0832GS

74AUP1G08 IBIS model 74AUP1G08GW

XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm NCX2200GS

Reversed product orientation 12NC ending 132 NTS0101

74AVCM162836DGG

74LVC2G17

©1993 - 2024 BDTIC