The 74AUP1G125 provides s single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input (OE) is HIGH.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
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Low-power buffer/line driver; 3-state (REV 6.0) PDF (372.0 kB) 74AUP1G125 [English] | 15 Aug 2012 |
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Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
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電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
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ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
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plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals (REV 1.0) PDF (199.0 kB) SOT1226 [English] | 08 Feb 2016 |
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X2SON5; Reel pack SMD 7" Q3/T4 standard product orientation Orderable part number ending ,125 or H Ordering... (REV 1.0) PDF (97.0 kB) SOT1226_125 [English] | 09 Aug 2016 |
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MAR_SOT1226 Topmark (REV 1.0) PDF (35.0 kB) MAR_SOT1226 [English] | 03 Jun 2013 |
Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Package version | Output drive capability (mA) | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74AUP1G125GX | Active | AUP | 1.1 - 3.6 | Buffers/inverters/drivers | single buffer/line driver (3-state) | CMOS | SOT1226 | +/- 1.9 | 70 | 1 | 4.3 | ultra low | -40~125 | 322 | 90.7 | 191 | X2SON5 | 5 |
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
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74AUP1G125GX | SOT1226 | Reel 7" Q3/T4, Reverse | Active | 74AUP1G125GX,125 (9352 983 68125) | pM | 74AUP1G125GX | Always Pb-free | 1 | 1 |