The 74AUP1G132 provides the single 2-input NAND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
Name/Description | Modified Date |
---|---|
Low-power 2-input NAND Schmitt trigger (REV 5.0) PDF (362.0 kB) 74AUP1G132 [English] | 29 Jun 2012 |
Name/Description | Modified Date |
---|---|
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English] | 30 Dec 2010 |
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Name/Description | Modified Date |
---|---|
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Name/Description | Modified Date |
---|---|
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Name/Description | Modified Date |
---|---|
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm (REV 1.0) PDF (189.0 kB) SOT886 [English] | 08 Feb 2016 |
Name/Description | Modified Date |
---|---|
XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... (REV 2.0) PDF (205.0 kB) SOT886_115 [English] | 23 Apr 2013 |
XSON6; reel pack; standard product orientation; 12NC ending 132 (REV 1.0) PDF (180.0 kB) SOT886_132 [English] | 28 Nov 2012 |
Name/Description | Modified Date |
---|---|
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English] | 30 Sep 2013 |
MAR_SOT886 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT886 [English] | 03 Jun 2013 |
Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Type | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74AUP1G132GM | Active | AUP | NAND gates | 1.1 - 3.6 | CMOS | single 2-input NAND gate Schmitt-trigger | NAND gates | +/- 1.9 | SOT886 | 10 | 70 | 1 | ultra low | -40~125 | 311 | 7.7 | 157 | XSON6 | 6 |
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74AUP1G132GM | SOT886 | Reflow_Soldering_Profile | Reel 7" Q1/T1, Q3/T4 | Active | 74AUP1G132GM,132 (9352 790 59132) | aE | 74AUP1G132GM | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 | ||
Reel 7" Q1/T1 | Active | 74AUP1G132GM,115 (9352 790 59115) | aE | 74AUP1G132GM | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |