74AUP1G175GW-Q100: Low-power D-type flip-flop with reset; positive-edge trigger
The 74AUP1G175-Q100 provides a low-power, low-voltage positive-edge triggered
D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input,
and Q output. The master reset (MR) is an asynchronous active LOW input and operates
independently of the clock input. Information on the data input is transferred to the
Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable
one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
74AUP1G175GW-Q100: Product Block Diagram
SOT363
Data Sheets (1)
Application Notes (2)
Brochures (2)
Selector Guides (2)
Package Information (1)
Packing (1)
Supporting Information (3)
Ordering Information
| Product | Status | Family | VCC (V) | Description | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74AUP1G175GW-Q100 | Active | AUP | 1.1 - 3.6 | single D flip-flop with reset | CMOS | +/- 1.9 | 7.4 | 70 | ultra low | -40~125 | 264 | 38.6 | 153 | TSSOP6 | 6 | SOT363 |
Package Information
