74AUP1G17GW: Low-power Schmitt trigger
The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
74AUP1G17GW: Product Block Diagram
Outline 3d SOT353-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power Schmitt trigger (REV 8.0) PDF (235.0 kB) 74AUP1G17 [English] | 15 Jan 2015 |
Application Notes (3)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 5 leads; body width 1.25 mm (REV 1.0) PDF (223.0 kB) SOT353-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... (REV 1.0) PDF (257.0 kB) SOT353-1_125 [English] | 15 May 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT353 Topmark (REV 1.0) PDF (103.0 kB) MAR_SOT353 [English] | 03 Jun 2013 |
IBIS Model
- 74AUP1G17 IBIS model (REV 1.0)Updated ibs AUP1G17 10/28/2016
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G17GW | Active | AUP | 1.1 - 3.6 | Schmitt-triggers | single buffer Schmitt-trigger | CMOS | +/- 1.9 | SOT353-1 | 7.8 | 70 | 1 | ultra Low | -40~125 | 309 | 79.2 | 179 | TSSOP5 | 5 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G17GW | | SOT353-1 | Reel 7" Q3/T4, Reverse | Active | 74AUP1G17GW,125 (9352 790 24125) | pJ | 74AUP1G17GW |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
- Low-power Schmitt trigger 74AUP1G17GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- PicoGate Logic footprints NX3L4684
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- MAR_SOT353 Topmark 74LVC1G17_Q100
- 74AUP1G17 IBIS model 74AUP1G17GW
- plastic thin shrink small outline package; 5 leads; body width 1.25 mm 74LVC1G17_Q100
- TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... 74LVC1G17_Q100
- 74AUP1G17
- XC7SH14
