74AUP1G17GX: Low-power Schmitt trigger

The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

74AUP1G17GX: Product Block Diagram
sot1226_3d
Data Sheets (1)
Name/DescriptionModified Date
Low-power Schmitt trigger (REV 8.0) PDF (235.0 kB) 74AUP1G17 [English]15 Jan 2015
Application Notes (1)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals (REV 1.0) PDF (199.0 kB) SOT1226 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
X2SON5; Reel pack SMD 7" Q3/T4 standard product orientation Orderable part number ending ,125 or H Ordering... (REV 1.0) PDF (97.0 kB) SOT1226_125 [English]09 Aug 2016
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT1226 Topmark (REV 1.0) PDF (35.0 kB) MAR_SOT1226 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)DescriptionLogic switching levelsOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1G17GXActiveAUPSchmitt-triggers1.1 - 3.6single buffer Schmitt-triggerCMOS+/- 1.9SOT12267.8701ultra Low-40~12532290.7191X2SON55
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AUP1G17GXSOT1226Reel 7" Q3/T4, ReverseActive74AUP1G17GX,125 (9352 982 28125)pJ74AUP1G17GXAlways Pb-free11
Low-power Schmitt trigger 74AUP1G17GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
X2SON5; Reel pack SMD 7" Q3/T4 standard product orientation Orderable part number ending ,125 or H Ordering... 74AUP1G32
MAR_SOT1226 Topmark 74AUP1G32
74AUP1G17 IBIS model 74AUP1G17GW
SOT1226 74AUP1G32
74AVCM162836DGG
74LVC1G17