74AUP1G3208GF: Low-power 3-input OR-AND gate
The 74AUP1G3208 provides the Boolean function: Y = (A + B) x C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74AUP1G3208GF: Product Block Diagram
Outline 3d SOT891
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power 3-input OR-AND gate (REV 6.0) PDF (189.0 kB) 74AUP1G3208 [English] | 09 Mar 2016 |
Application Notes (3)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm (REV 1.0) PDF (185.0 kB) SOT891 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| XSON6; reel pack; standard product orientation; 12NC ending 132 (REV 1.0) PDF (180.0 kB) SOT891_132 [English] | 26 Aug 2014 |
Supporting Information (2)
| Name/Description | Modified Date |
|---|---|
| Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English] | 30 Sep 2013 |
| MAR_SOT891 Topmark (REV 1.0) PDF (51.0 kB) MAR_SOT891 [English] | 03 Jun 2013 |
IBIS Model
- 74AUP1G3208 IBIS model (REV 1.0) ibs AUP1G3208 2/25/2016
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Type | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G3208GF | Active | AUP | 1.1 - 3.6 | Combination | CMOS | single 3-input OR-AND gate | Combination gates | +/- 1.9 | SOT891 | 7.4 | 70 | 1 | ultra low | -40~125 | 290 | 6.5 | 145 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G3208GF | | SOT891 | Reflow_Soldering_Profile | Reel 7" Q1/T1, Q3/T4 | Active | 74AUP1G3208GF,132 (9352 813 23132) | a2 | 74AUP1G3208GF |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
- Low-power 3-input OR-AND gate 74AUP1G3208GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- PicoGate Logic footprints NX3L4684
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- MAR_SOT891 Topmark prtr5v0u2k
- 74AUP1G3208 IBIS model 74AUP1G3208GW
- XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm prtr5v0u2k
- Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
- XSON6; reel pack; standard product orientation; 12NC ending 132 prtr5v0u2k
- 74AUP1G3208
- BGU7003
