74AUP1G373GW-Q100: Low-power D-type transparent latch; 3-state
The 74AUP1G373-Q100 provides the single D-type transparent latch with 3-state output.
While the latch-enable (LE) input is high, the Q output follows the data (D) input. When
pin LE is LOW, the latch stores the information that was present at the D-input one set-up
time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents
of the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the
high-impedance OFF-state. Operation of input pin OE does not affect the state of the
latch. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and
fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
74AUP1G373GW-Q100: Product Block Diagram
SOT363
Data Sheets (1)
Application Notes (1)
Brochures (2)
Selector Guides (2)
Package Information (1)
Packing (1)
Supporting Information (3)
Ordering Information
| Product | Status | VCC (V) | Family | Logic switching levels | Description | Output drive capability (mA) | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74AUP1G373GW-Q100 | Active | 1.1 - 3.6 | AUP | CMOS | single D-type transparent latch (3-state) | 1.9/-1.9 | 8.5 | 1 | ultra low | -40~125 | 250 | 69.0 | | TSSOP6 | 6 | SOT363 |
Package Information
