74AUP1G386GW: Low-power 3-input EXCLUSIVE-OR gate _ BDTIC a Leading Distributor in China

74AUP1G386GW: Low-power 3-input EXCLUSIVE-OR gate

The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP1G386GW: Product Block Diagram

SOT363

Data Sheets (1)

Name/Description	Modified Date
Low-power 3-input EXCLUSIVE-OR gate (REV 6.0) PDF (197.0 kB) 74AUP1G386 [English]	31 Jul 2012

Application Notes (3)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]	06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]	30 Oct 2002

Brochures (3)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic surface-mounted package; 6 leads (REV 1.0) PDF (246.0 kB) SOT363_1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (188.0 kB) SOT363_125 [English]	20 Nov 2012

Supporting Information (3)

Name/Description	Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]	30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]	30 Sep 2013
MAR_SOT363 Topmark (REV 1.0) PDF (104.0 kB) MAR_SOT363 [English]	03 Jun 2013

IBIS Model

aup1g386 IBIS model (REV 2.0) ibs AUP1G386 12/22/2014
74AUP1G38 IBIS model (REV 1.0) ibs AUP1G38 12/15/2014

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Description	Type	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP1G386GW	Active	AUP	1.1 - 3.6	EXCLUSIVE-OR gates	CMOS	single 3-input EXCLUSIVE-OR gate	EXCLUSIVE-OR gates	+/- 1.9	SOT363	8.6	70	1	ultra low	-40~125	264	38.6	153	TSSOP6	6

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74AUP1G386GW		SOT363	Reflow_Soldering_Profile Wave_Soldering_Profile Reflow_Soldering_Profile Wave_Soldering_Profile	Reel 7" Q3/T4, Reverse	Active	74AUP1G386GW,125 (9352 800 05125)	aH	74AUP1G386GW		Always Pb-free	0.0	3.29	3.04E8	1	1