74AUP1G74GT: Low-power D-type flip-flop with set and reset; positive-edge trigger
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74AUP1G74GT: Product Block Diagram
Outline 3d SOT833-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power D-type flip-flop with set and reset; positive-edge trigger (REV 10.0) PDF (267.0 kB) 74AUP1G74 [English] | 28 Oct 2016 |
Application Notes (3)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm (REV 1.0) PDF (201.0 kB) SOT833-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Standard product orientation 12NC ending 115 (REV 3.0) PDF (88.0 kB) SOT833-1_115 [English] | 05 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT833 Topmark (REV 1.0) PDF (75.0 kB) MAR_SOT833 [English] | 03 Jun 2013 |
IBIS Model
- aup1g74 IBIS model (REV 1.1) ibs AUP1G74 4/8/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G74GT | Active | AUP | D-type flip-flops | 1.1 - 3.6 | CMOS | positive-edge trigger | +/- 1.9 | SOT833-1 | 9.2 | 400 | ultra low | -40~125 | 327 | 6.1 | 157 | XSON8 | 8 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G74GT | | SOT833-1 | Reel 7" Q1/T1 | Active | 74AUP1G74GT,115 (9352 807 18115) | p74 | 74AUP1G74GT |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- PicoGate Logic footprints NX3L4684
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- MAR_SOT833 Topmark NCX2222
- aup1g74 IBIS model 74AUP1G74GT
- plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm NCX2222
- Standard product orientation 12NC ending 115 NCX2222
- 74AUP1G74
- XC7WT14
