74AUP1G74GX: Low-power D-type flip-flop with set and reset; positive-edge trigger
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Data Sheets (1)
Package Information (1)
Packing (1)
Ordering Information
| Product | Status | VCC (V) | Family | Logic switching levels | Description | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74AUP1G74GX | Introduction Pending | 1.1 - 3.6 | AUP | CMOS | single D-type flip-flop with set and reset | +/- 1.9 | 9.2 | 400 | ultra low | -40~125 | | | | X2SON8 | 8 | SOT1233 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF |
|---|
| 74AUP1G74GX |  | SOT1233 | | Reel 7" Q1/T1 | Development | 74AUP1G74GXX
(9353 084 41115) | Standard Marking | | |
