74AUP1T34GN: Low-power dual supply translating buffer
The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC(A). Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y) accepts any supply voltage from 1.1 V to 3.6 V. This feature allows universal low voltage interfacing between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 1.1 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 1.1 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74AUP1T34GN: Product Block Diagram
Outline 3d SOT1115
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power dual supply translating buffer (REV 5.0) PDF (386.0 kB) 74AUP1T34 [English] | 04 Sep 2013 |
Application Notes (1)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (4)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
| Application guide: Flat-panel TV sets (REV 2.1) PDF (3.2 MB) 75017085 [English] | 13 Mar 2012 |
| Application guide; Portable devices and mobile handsets (REV 2.0) PDF (15.4 MB) 75017090 [English] | 13 Mar 2012 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English] | 04 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English] | 03 Jun 2013 |
IBIS Model
- 74AUP1T34 IBIS model (REV 1.0) ibs AUP1T34 12/15/2014
Ordering Information
| Product | Status | Family | VCC(A) (V) | Function | Description | VCC(B) (V) | Logic switching levels | Package version | Output drive capability (mA) | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1T34GN | Active | AUP | 1.1 - 3.6 | Level shifters/translators | single dual supply translating buffer | 1.1 - 3.6 | CMOS | SOT1115 | +/- 1.9 | 15.2 | 1 | ultra low | -40~125 | 367 | 28.9 | 227 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1T34GN | | SOT1115 | Reel 7" Q1/T1, Q3/T4 | Active | 74AUP1T34GN,132 (9352 917 52132) | pQ | 74AUP1T34GN |    | Always Pb-free | 1 | 1 |
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