74AUP1T34GW: Low-power dual supply translating buffer

The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC(A). Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y) accepts any supply voltage from 1.1 V to 3.6 V. This feature allows universal low voltage interfacing between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 1.1 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 1.1 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP1T34GW: Product Block Diagram
Outline 3d SOT353-1
Data Sheets (1)
Name/DescriptionModified Date
Low-power dual supply translating buffer (REV 5.0) PDF (386.0 kB) 74AUP1T34 [English]04 Sep 2013
Application Notes (2)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
Brochures (2)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (4)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Application guide: Flat-panel TV sets (REV 2.1) PDF (3.2 MB) 75017085 [English]13 Mar 2012
Application guide; Portable devices and mobile handsets (REV 2.0) PDF (15.4 MB) 75017090 [English]13 Mar 2012
Package Information (1)
Name/DescriptionModified Date
plastic thin shrink small outline package; 5 leads; body width 1.25 mm (REV 1.0) PDF (223.0 kB) SOT353-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... (REV 1.0) PDF (257.0 kB) SOT353-1_125 [English]15 May 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT353 Topmark (REV 1.0) PDF (103.0 kB) MAR_SOT353 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyVCC(A) (V)FunctionVCC(B) (V)DescriptionLogic switching levelsPackage versionOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1T34GWActiveAUP1.1 - 3.6Level shifters/translators1.1 - 3.6single dual supply translating bufferCMOSSOT353-1+/- 1.915.21ultra low-40~12529265.6165TSSOP55
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AUP1T34GWSOT353-1Reel 7" Q3/T4, ReverseActive74AUP1T34GW,125 (9352 805 16125)pQ74AUP1T34GWAlways Pb-free11
Low-power dual supply translating buffer 74AUP1T34GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
Application guide: Flat-panel TV sets mmbz33vcl
Application guide; Portable devices and mobile handsets pesd24vs1ul
MAR_SOT353 Topmark 74LVC1G17_Q100
74AUP1T34 IBIS model 74AUP1T34GX
plastic thin shrink small outline package; 5 leads; body width 1.25 mm 74LVC1G17_Q100
TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... 74LVC1G17_Q100
74AUP1T34
XC7SH14