74AUP1T58GW: Low-power configurable gate with voltage-level translator
The 74AUP1T58 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.
The 74AUP1T58 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range.
74AUP1T58GW: Product Block Diagram
SOT363
Data Sheets (1)
Application Notes (2)
Brochures (2)
Selector Guides (2)
Package Information (1)
Packing (1)
Supporting Information (3)
IBIS Model
Ordering Information
Product | Status | Family | Function | VCC (V) | Logic switching levels | Type | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74AUP1T58GW | Active | AUP | Configurable multiple function gates | 2.3 - 3.6 | CMOS | Configurable gates | configurable gate with voltage level translation | +/- 1.9 | SOT363 | 8.7 | 70 | 1 | ultra low | -40~125 | 264 | 38.6 | 153 | TSSOP6 | 6 |
Package Information