74AUP1T97GN: Low-power configurable gate with voltage-level translator

The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.

The 74AUP1T97 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range.

74AUP1T97GN: Product Block Diagram
Outline 3d SOT1115
Data Sheets (1)
Name/DescriptionModified Date
Low-power configurable gate with voltage-level translator (REV 5.0) PDF (230.0 kB) 74AUP1T97 [English]17 Sep 2015
Application Notes (1)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Brochures (2)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English]04 Apr 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English]03 Jun 2013
Design Support
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsTypeDescriptionVCC(A) (V)Output drive capability (mA)Package versiontpd (ns)VCC(B) (V)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1T97GNActiveAUPConfigurable multiple function gates2.3 - 3.6CMOSConfigurable gatesconfigurable gate with voltage level translation1.1 - 3.6+/- 1.9SOT11158.71.1 - 3.6701ultra low-40~12527511.7171XSON66
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AUP1T97GNSOT1115Reel 7" Q1/T1, Q3/T4Active74AUP1T97GN,132 (9352 889 86132)5974AUP1T97GNAlways Pb-free11
Low-power configurable gate with voltage-level translator 74AUP1T97GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT1115 Topmark 74AUP1G332
Demonstrate seven different logic functions 74AUP1T97GW
aup1t97 IBIS model 74AUP1T97GW
SOT1115 74AUP1G332
Reel 7" Q1/T1, Q3/T4 74AUP1G332
74AVCM162836DGG
74LVC2G17