74AUP1Z04GW: Low-power X-tal driver with enable and internal transistor

The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in crystal oscillator applications.

When not in use the EN input can be driven HIGH, putting the device in a low power disable mode with X1 pulled HIGH via RPU, X2 set LOW and Y set HIGH. Schmitt trigger action at the EN input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF at output Y. The IOFF circuitry disables the output Y, preventing the damaging backflow current through the device when it is powered down.

The integration of the two devices into the 74AUP1Z04 produces the benefits of a compact footprint, lower power dissipation and stable operation over a wide range of frequency and temperature.

74AUP1Z04GW: Product Block Diagram

SOT363

Data Sheets (1)

Name/Description	Modified Date
Low-power X-tal driver with enable and internal transistor (REV 5.0) PDF (240.0 kB) 74AUP1Z04 [English]	09 Aug 2012

Application Notes (2)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]	30 Oct 2002

Brochures (4)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014
NXP® Logic Demo Board Kit (REV 1.0) PDF (1.4 MB) 75017059 [English]	02 Apr 2013
Easy test and evaluation of the 74AUP1Z04 (REV 1.0) PDF (2.3 MB) 75016907 [English]	12 Feb 2013

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic surface-mounted package; 6 leads (REV 1.0) PDF (246.0 kB) SOT363_1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (188.0 kB) SOT363_125 [English]	20 Nov 2012

Supporting Information (3)

Name/Description	Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]	30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]	30 Sep 2013
MAR_SOT363 Topmark (REV 1.0) PDF (104.0 kB) MAR_SOT363 [English]	03 Jun 2013

IBIS Model

aup1z04 IBIS model (REV 2.0) ibs AUP1Z04 12/22/2014

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Description	Type	Package version	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP1Z04GW	Active	AUP	1.1 - 3.6	Combination	CMOS	crystal driver with enable and internal resistor	Combination gates	SOT363	+/- 1.9	5.6	70	2	ultra low	-40~125	264	38.6	153	TSSOP6	6

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	MSL	MSL LF
74AUP1Z04GW		SOT363	Reflow_Soldering_Profile Wave_Soldering_Profile Reflow_Soldering_Profile Wave_Soldering_Profile	Reel 7" Q3/T4, Reverse	Active	74AUP1Z04GW,125 (9352 805 19125)	a4	74AUP1Z04GW		Always Pb-free	1	1