74AUP2G00GX: Low-power dual 2-input NAND gate
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Data Sheets (1)
Package Information (1)
Packing (1)
Ordering Information
| Product | Status | VCC (V) | Family | Type | Logic switching levels | Output drive capability (mA) | Description | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74AUP2G00GX | Introduction Pending | 1.1 - 3.6 | AUP | NAND gates | CMOS | +/- 1.9 | dual 2-input NAND gate | 8.3 | 70 | 2 | ultra low | -40~125 | | | | X2SON8 | 8 | SOT1233 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF |
|---|
| 74AUP2G00GX |  | SOT1233 | | Reel 7" Q1/T1 | Development | 74AUP2G00GXX
(9353 084 39115) | Standard Marking | | |
