74AUP2G07GW: Low-power dual buffer with open-drain output
The 74AUP2G07 provides two non-inverting buffers with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74AUP2G07GW: Product Block Diagram
SOT363
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power dual buffer with open-drain output (REV 8.0) PDF (202.0 kB) 74AUP2G07 [English] | 17 Sep 2015 |
Application Notes (3)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic surface-mounted package; 6 leads (REV 1.0) PDF (246.0 kB) SOT363_1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (188.0 kB) SOT363_125 [English] | 20 Nov 2012 |
Supporting Information (3)
| Name/Description | Modified Date |
|---|---|
| Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English] | 30 Sep 2013 |
| Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English] | 30 Sep 2013 |
| MAR_SOT363 Topmark (REV 1.0) PDF (104.0 kB) MAR_SOT363 [English] | 03 Jun 2013 |
IBIS Model
- aup2g07 IBIS model (REV 1.0) ibs AUP2G07 9/7/2015
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Package version | Output drive capability (mA) | fmax (MHz) | No of bits | Power dissipation considerations | tpd (ns) | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G07GW | Active | AUP | Buffers/inverters/drivers | 1.1 - 3.6 | CMOS | open-drain | SOT363 | 1.9 | 70 | 2 | ultra low | 4.4 | -40~125 | 264 | 38.6 | 153 | TSSOP6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G07GW | | SOT363 | Reflow_Soldering_Profile
Wave_Soldering_Profile Reflow_Soldering_Profile Wave_Soldering_Profile | Reel 7" Q3/T4, Reverse | Active | 74AUP2G07GW,125 (9352 799 85125) | p7 | 74AUP2G07GW |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
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- PicoGate Logic footprints NX3L4684
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- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- MAR_SOT363 Topmark BSS84AKS
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- plastic surface-mounted package; 6 leads BSS84AKS
- Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
- Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
- Tape reel SMD; reversed product orientation 12NC ending 125 74LVC2G17_Q100
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