74AUP2G132GN: Low-power dual 2-input NAND Schmitt trigger _ BDTIC a Leading Distributor in China

74AUP2G132GN: Low-power dual 2-input NAND Schmitt trigger

The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accepts standard input signals. They can transform slowly changing input signals into sharply defined, jitter-free output signals.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

74AUP2G132GN: Product Block Diagram

Outline 3d SOT1116

Data Sheets (1)

Name/Description	Modified Date
low-power dual 2-input NAND Schmitt trigger (REV 7.0) PDF (290.0 kB) 74AUP2G132 [English]	08 Feb 2013

Application Notes (2)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]	06 May 2011

Brochures (3)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
extremely thin small outline package; no leads; 8 terminals (REV 1.0) PDF (188.0 kB) SOT1116 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Standard product orientation 12NC ending 115 (REV 2.0) PDF (88.0 kB) SOT1116_115 [English]	04 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
MAR_SOT1116 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT1116 [English]	03 Jun 2013

IBIS Model

aup2g132 IBIS model (REV 1.0) ibs AUP2G132 4/7/2013

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Description	Type	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP2G132GN	Active	AUP	1.1 - 3.6	Schmitt-triggers	CMOS	dual 2-input NAND gate Schmitt-trigger	NAND gates	+/- 1.9	SOT1116	10	70	2	ultra Low	-40~125	238	10.6	148	XSON8	8

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	MSL	MSL LF
74AUP2G132GN		SOT1116		Reel 7" Q1/T1	Active	74AUP2G132GN,115 (9352 922 22115)	aE	74AUP2G132GN		Always Pb-free	1	1

low-power dual 2-input NAND Schmitt trigger 74AUP2G132GT

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

Pin FMEA for AUP family 74AUP1T34GW-Q100

電圧レベルシフタ 74AVC16245DGG-Q100

NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100

Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100

ロジック製品セレクションガイド... 74LVC_H_245A_Q100

Logic selection guide 2016 74LVC_H_245A_Q100

MAR_SOT1116 Topmark 74AXP2T3407GN

aup2g132 IBIS model 74AUP2G132GT

SOT1116 74AXP2T3407GN

Reel 7" Q1/T1 74AXP2T3407GN

74AVCM162836DGG

74LVC3G17

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