74AUP2G14GM: Low-power dual Schmitt trigger inverter
The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
74AUP2G14GM: Product Block Diagram
Outline 3d SOT886
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power dual Schmitt trigger inverter (REV 6.0) PDF (240.0 kB) 74AUP2G14 [English] | 17 Sep 2015 |
Application Notes (4)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English] | 30 Dec 2010 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm (REV 1.0) PDF (189.0 kB) SOT886 [English] | 08 Feb 2016 |
Packing (2)
| Name/Description | Modified Date |
|---|---|
| XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... (REV 2.0) PDF (205.0 kB) SOT886_115 [English] | 23 Apr 2013 |
| XSON6; reel pack; standard product orientation; 12NC ending 132 (REV 1.0) PDF (180.0 kB) SOT886_132 [English] | 28 Nov 2012 |
Supporting Information (2)
| Name/Description | Modified Date |
|---|---|
| Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English] | 30 Sep 2013 |
| MAR_SOT886 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT886 [English] | 03 Jun 2013 |
IBIS Model
- aup2g14 IBIS model (REV 1.0) ibs AUP2G14 9/7/2015
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G14GM | Active | AUP | 1.1 - 3.6 | Schmitt-triggers | CMOS | dual inverter Schmitt-trigger | SOT886 | +/- 1.9 | 4.7 | 70 | 2 | ultra low | -40~125 | 290 | 6.5 | 145 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G14GM | | SOT886 | Reflow_Soldering_Profile | Reel 7" Q1/T1, Q3/T4 | Active | 74AUP2G14GM,132 (9352 799 88132) | pK | 74AUP2G14GM |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
| Reel 7" Q1/T1 | Active | 74AUP2G14GM,115 (9352 799 88115) | pK | 74AUP2G14GM | | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
- Low-power dual Schmitt trigger inverter 74AUP2G14GX
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- MicroPak soldering information NTS0102_Q100
- PicoGate Logic footprints NX3L4684
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- MAR_SOT886 Topmark prtr5v0u2f
- aup2g14 IBIS model 74AUP2G14GW
- XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm prtr5v0u2f
- Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
- XSON6; reel pack; standard product orientation; 12NC ending 132 NCX2200GM
- XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... prtr5v0u2f
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