74AUP2G241GF: Low-power dual buffer/line driver; 3-state

The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This device has an input-disable feature, which allows floating input signals. The input 1A is disabled when the output enable input 1OE is HIGH. The input 2A is disabled when the output enable input 2OE is LOW.

74AUP2G241GF: Product Block Diagram
Outline 3d SOT1089
Data Sheets (1)
Name/DescriptionModified Date
Low-power dual buffer/line driver; 3-state (REV 7.0) PDF (302.0 kB) 74AUP2G241 [English]11 Feb 2013
Application Notes (2)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
extremely thin small outline package; no leads; 8 terminals (REV 1.0) PDF (200.0 kB) SOT1089 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
XSON8; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... (REV 3.0) PDF (205.0 kB) SOT1089_115 [English]23 Apr 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT1089 Topmark (REV 1.0) PDF (76.0 kB) MAR_SOT1089 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionPackage versionOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationstpd (ns)Tamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G241GFActiveAUPBuffers/inverters/drivers1.1 - 3.6CMOSdual buffer/line driver (3-state)SOT1089+/- 1.9702ultra low4.3-40~1252542.1124XSON88
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AUP2G241GFSOT1089Reel 7" Q1/T1Active74AUP2G241GF,115 (9352 914 81115)p174AUP2G241GFAlways Pb-free11
Low-power dual buffer/line driver; 3-state 74AUP2G241GT
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT1089 Topmark pca9306
aup2g241 IBIS model 74AUP2G241GT
extremely thin small outline package; no leads; 8 terminals pca9306
XSON8; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... pca9306
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