74AUP2G34GM: Low-power dual buffer

The 74AUP2G34 provides two low-power, low-voltage buffers.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP2G34GM: Product Block Diagram
Outline 3d SOT886
Data Sheets (1)
Name/DescriptionModified Date
Low-power dual buffer (REV 6.0) PDF (203.0 kB) 74AUP2G34 [English]17 Sep 2015
Application Notes (4)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]30 Dec 2010
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Package Information (1)
Name/DescriptionModified Date
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm (REV 1.0) PDF (189.0 kB) SOT886 [English]08 Feb 2016
Packing (2)
Name/DescriptionModified Date
XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... (REV 2.0) PDF (205.0 kB) SOT886_115 [English]23 Apr 2013
XSON6; reel pack; standard product orientation; 12NC ending 132 (REV 1.0) PDF (180.0 kB) SOT886_132 [English]28 Nov 2012
Supporting Information (2)
Name/DescriptionModified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]30 Sep 2013
MAR_SOT886 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT886 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionPackage versionOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationstpd (ns)Tamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G34GMActiveAUPBuffers/inverters/drivers1.1 - 3.6CMOSdual bufferSOT886+/- 1.9702ultra low3.9-40~1252906.5145XSON66
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74AUP2G34GMSOT886Reflow_Soldering_ProfileReel 7" Q1/T1, Q3/T4Active74AUP2G34GM,132 (9352 799 95132)aA74AUP2G34GMAlways Pb-free0.03.293.04E811
Reel 7" Q1/T1Active74AUP2G34GM,115 (9352 799 95115)aA74AUP2G34GMAlways Pb-free0.03.293.04E811
Low-power dual buffer 74AUP2G34GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
MicroPak soldering information NTS0102_Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
MAR_SOT886 Topmark prtr5v0u2f
aup2g34 IBIS model 74AUP2G34GW
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm prtr5v0u2f
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
XSON6; reel pack; standard product orientation; 12NC ending 132 NCX2200GM
XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... prtr5v0u2f
74LVC2G34
BGU8007