74AUP2G38GM: Low-power dual 2-input NAND gate; open drain
The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
74AUP2G38GM: Product Block Diagram
Outline 3d SOT902-2
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power dual 2-input NAND gate; open drain (REV 8.0) PDF (274.0 kB) 74AUP2G38 [English] | 11 Feb 2013 |
Application Notes (3)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| Plastic extremely thin quad flat package; no leads; 8 terminals (REV 1.3) PDF (206.0 kB) SOT902-2 [English] | 14 Jul 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| XQFN8(U); Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 1.0) PDF (201.0 kB) SOT902-2_125 [English] | 02 May 2013 |
IBIS Model
- aup2g38 IBIS model (REV 1.1) ibs AUP2G38 4/8/2013
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Type | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G38GM | Active | AUP | 1.1 - 3.6 | NAND gates | CMOS | open-drain | NAND gates | 1.9 | SOT902-2 | 8.5 | 70 | 2 | ultra low | -40~125 | 245 | 16.2 | 134 | XQFN8 | 8 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G38GM | | SOT902-2 | Reel 7" Q3/T4, Reverse | Active | 74AUP2G38GM,125 (9352 814 27125) | a38 | 74AUP2G38GM |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
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