74AUP2G79GT: Low-power dual D-type flip-flop; positive-edge trigger

The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

74AUP2G79GT: Product Block Diagram
Outline 3d SOT833-1
Data Sheets (1)
Name/DescriptionModified Date
Low-power dual D-type flip-flop; positive-edge trigger (REV 8.0) PDF (291.0 kB) 74AUP2G79 [English]24 Jan 2013
Application Notes (4)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]30 Dec 2010
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm (REV 1.0) PDF (201.0 kB) SOT833-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Standard product orientation 12NC ending 115 (REV 3.0) PDF (88.0 kB) SOT833-1_115 [English]05 Apr 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT833 Topmark (REV 1.0) PDF (75.0 kB) MAR_SOT833 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyVCC (V)FunctionDescriptionLogic switching levelsPackage versionOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G79GTActiveAUP1.1 - 3.6D-type flip-flopspositive-edge triggerCMOSSOT833-1+/- 1.98.5400ultra low-40~1253276.1157XSON88
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74AUP2G79GTSOT833-1Reel 7" Q1/T1Active74AUP2G79GT,115 (9352 807 21115)p7974AUP2G79GTAlways Pb-free0.03.293.04E811
Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G79GT
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
MicroPak soldering information NTS0102_Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT833 Topmark NCX2222
aup2g79 IBIS model 74AUP2G79GT
plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm NCX2222
Standard product orientation 12NC ending 115 NCX2222
74AUP2G79
XC7WT14