74AUP2G80GN: Low-power dual D-type flip-flop; positive-edge trigger
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
74AUP2G80GN: Product Block Diagram
Outline 3d SOT1116
Data Sheets (1)
Application Notes (2)
Brochures (3)
Selector Guides (2)
Package Information (1)
Packing (1)
Supporting Information (1)
Name/Description | Modified Date |
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MAR_SOT1116 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT1116 [English] | 03 Jun 2013 |
IBIS Model
Ordering Information
Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74AUP2G80GN | Active | AUP | D-type flip-flops | 1.1 - 3.6 | CMOS | positive-edge trigger | +/- 1.9 | SOT1116 | 9.1 | 400 | ultra low | -40~125 | 238 | 10.6 | 148 | XSON8 | 8 |
Package Information
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
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74AUP2G80GN | | SOT1116 | | Reel 7" Q1/T1 | Active | 74AUP2G80GN,115
(9352 922 29115) | pT | 74AUP2G80GN | | Always Pb-free | 1 | 1 |