74AUP3G14DC: Low-power triple Schmitt trigger inverter
The 74AUP3G14 provides three inverting buffers with Schmitt trigger action which accept
standard input signals. They are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow
current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The
difference between the positive voltage VT+ and the negative voltage
VT- is defined as the input hysteresis voltage VH.
Outline 3d SOT765-1
Data Sheets (1)
Package Information (1)
Packing (1)
IBIS Model
Ordering Information
| Product | Status | Family | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74AUP3G14DC | Active | AUP | 1.1 - 3.6 | CMOS | Schmitt-trigger | +/- 1.9 | 70 | 3 | 4.7 | ultra low | -40~125 | 203 | 34.1 | 113 | VSSOP8 | 8 | SOT765-1 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|
| 74AUP3G14DC | | SOT765-1 | | Reel 7" Q3/T4, Reverse | Active | 74AUP3G14DCH
(9352 807 01125) | Standard Marking | 74AUP3G14DC |    | Always Pb-free | 1 | 1 |
