74AUP3G3404GT: Low-power dual buffer and single inverter _ BDTIC a Leading Distributor in China

74AUP3G3404GT: Low-power dual buffer and single inverter

The 74AUP3G3404 is a dual buffer and single inverter.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

74AUP3G3404GT: Product Block Diagram

Outline 3d SOT833-1

Data Sheets (1)

Name/Description	Modified Date
Low-power dual buffer and single inverter (REV 1.0) PDF (316.0 kB) 74AUP3G3404 [English]	14 Jan 2013

Application Notes (2)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]	30 Dec 2010

Brochures (3)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm (REV 1.0) PDF (201.0 kB) SOT833-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Standard product orientation 12NC ending 115 (REV 3.0) PDF (88.0 kB) SOT833-1_115 [English]	05 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
MAR_SOT833 Topmark (REV 1.0) PDF (75.0 kB) MAR_SOT833 [English]	03 Jun 2013

IBIS Model

IBIS model (REV 1.0) ibs AUP3G3404 6/4/2014

Ordering Information

Product	Status	Family	Function	V_CC (V)	Logic switching levels	Type	Description	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP3G3404GT	Active	AUP	Combination	1.1 - 3.6	CMOS	Combination gates	dual buffer and single inverter	+/- 1.9	SOT833-1	4	70	3	ultra low	-40~125	327	6.1	157	XSON8	8

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	MSL	MSL LF
74AUP3G3404GT		SOT833-1		Reel 7" Q1/T1	Active	74AUP3G3404GTX (9352 994 53115)	aZ	74AUP3G3404GT		Always Pb-free	1	1

Low-power dual buffer and single inverter 74AUP3G3404GT

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

MicroPak soldering information NTS0102_Q100

電圧レベルシフタ 74AVC16245DGG-Q100

NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100

Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100

ロジック製品セレクションガイド... 74LVC_H_245A_Q100

Logic selection guide 2016 74LVC_H_245A_Q100

MAR_SOT833 Topmark NCX2222

IBIS model 74AUP3G3404GT

plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm NCX2222

Standard product orientation 12NC ending 115 NCX2222

74AVCM162836DGG

XC7WT14

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