74AUP3G34GM: Low-power triple buffer
The 74AUP3G34 is a triple buffer.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
74AUP3G34GM: Product Block Diagram
Outline 3d SOT902-2
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power triple buffer (REV 2.0) PDF (215.0 kB) 74AUP3G34 [English] | 12 Oct 2016 |
Application Notes (2)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| Plastic extremely thin quad flat package; no leads; 8 terminals (REV 1.3) PDF (206.0 kB) SOT902-2 [English] | 14 Jul 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| XQFN8(U); Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 1.0) PDF (201.0 kB) SOT902-2_125 [English] | 02 May 2013 |
IBIS Model
- 74AUP3G34 IBIS Model (REV 1.0) ibs AUP3G34 12/5/2014
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Output drive capability (mA) | Package version | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP3G34GM | Active | AUP | 1.1 - 3.6 | triple buffer | CMOS | triple buffer | +/- 1.9 | SOT902-2 | 70 | 3 | 3.9 | ultra low | -40~125 | 251 | 128.0 | XQFN8 | 8 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP3G34GM | | SOT902-2 | Reel 7" Q3/T4, Reverse | Active | 74AUP3G34GM,125 (9352 814 45125) | Standard Marking | 74AUP3G34GM |    | week 36, 2014 | 1 | 1 |
- Low-power triple buffer 74AUP3G34GT
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- 74AUP3G34 IBIS Model 74AUP3G34GT
- Plastic extremely thin quad flat package; no leads; 8 terminals pca9509agm
- XQFN8(U); Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... pca9509agm
- 74AVCM162836DGG
- 74LVC3G17
