74CBTLV3126DS: 4-bit bus switch
The 74CBTLV3126 provides a 4-bit high-speed bus switch with separate output enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is LOW.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the GND through a pull-down resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
sot519-1_3d
Data Sheets (1)
Name/Description | Modified Date |
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4-bit bus switch (REV 3.0) PDF (156.0 kB) 74CBTLV3126 [English] | 20 Dec 2011 |
Brochures (2)
Package Information (1)
Packing (1)
Supporting Information (2)
IBIS Model
Ordering Information
Product | Status | Family | Function | VCC (V) | VPASS (V) | Description | Logic switching levels | Package version | RON (Ohm) | f(-3dB) (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74CBTLV3126DS | Active | CBTLV(D) | quad bus switch | 2.3 - 3.6 | 3.3 | quad bus switch | CMOS / LVTTL | SOT519-1 | 7 | 400 | 4 | 0.2 | very Low | -40~125 | 148 | 42.0 | | SSOP16 | 16 |
Package Information