74HC161DB: Presettable synchronous 4-bit binary counter; asynchronous reset

The 74HC/1 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT161 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP).

The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET).

A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

fmax= (1) / (tP(max)(CP to TC) + tSU(CEP to CP) )

74HC161DB: Product Block Diagram

Outline 3d SOT338-1

Data Sheets (1)

Name/Description	Modified Date
Presettable synchronous 4-bit binary counter; asynchronous reset (REV 1.0) PDF (80.0 kB) 74HC_HCT161_CNV [English]	01 Dec 1990

Application Notes (2)

Name/Description	Modified Date
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Pin FMEA 74HC/74HCT family (REV 1.0) PDF (51.0 kB) AN11044 [English]	16 Mar 2011

Users Guides (1)

Name/Description	Modified Date
HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English]	01 Nov 1997

Package Information (1)

Name/Description	Modified Date
plastic shrink small outline package; 16 leads; body width 5.3 mm (REV 1.0) PDF (306.0 kB) SOT338-1 [English]	08 Feb 2016

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

SPICE model

hc Spice model (REV 1.0) ZIP HC 5/7/2013

Ordering Information

Product	Status	Family	Function	V_CC (V)	Description	Output drive capability (mA)	Logic switching levels	Package version	t_pd (ns)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74HC161DB	Active	HC(T)	Binary counters/timers	2.0 - 6.0	asynchronous reset	+/- 5.2	CMOS	SOT338-1	19	low	-40~125	148	42.0		SSOP16	16

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74HC161DB		SOT338-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74HC161DB,118 (9351 745 10118)	HC161	74HC161DB		week 12, 2005	84.9	6.62	1.51E8	1	1
74HC161DB		SOT338-1		Bulk Pack	Active	74HC161DB,112 (9351 745 10112)	HC161	74HC161DB		week 12, 2005	84.9	6.62	1.51E8	1	1