74HC163D: Presettable synchronous 4-bit binary counter; synchronous reset

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula:

fmax= (1) / (tP (max)(CP to TC) + tSU(CEP to CP) )

74HC163D: Product Block Diagram

sot109-1_3d

Data Sheets (1)

Name/Description	Modified Date
Presettable synchronous 4-bit binary counter; synchronous reset (REV 4.0) PDF (240.0 kB) 74HC_HCT163 [English]	28 Dec 2015

Application Notes (2)

Name/Description	Modified Date
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Pin FMEA 74HC/74HCT family (REV 1.0) PDF (51.0 kB) AN11044 [English]	16 Mar 2011

Users Guides (1)

Name/Description	Modified Date
HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English]	01 Nov 1997

Package Information (1)

Name/Description	Modified Date
plastic small outline package; 16 leads; body width 3.9 mm (REV 1.0) PDF (192.0 kB) SOT109-1 [English]	08 Feb 2016

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]	08 Oct 2009

SPICE model

hc Spice model (REV 1.0) ZIP HC 5/7/2013

Ordering Information

Product	Status	Family	V_CC (V)	Function	Output drive capability (mA)	Description	Package version	Logic switching levels	t_pd (ns)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74HC163D	Active	HC(T)	2.0 - 6.0	Binary counters/timers	+/- 5.2	synchronous reset	SOT109-1	CMOS	17	low	-40~125	83	5.2	41	SO16	16

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74HC163D		SOT109-1	SO-SOJ-REFLOW SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE	Reel 13" Q1/T1 CECC	Active	74HC163D,653 (9337 145 40653)	74HC163D	74HC163D		week 6, 2004	84.9	6.62	1.51E8	1	1
74HC163D		SOT109-1	SO-SOJ-REFLOW SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE	Bulk Pack, CECC	Active	74HC163D,652 (9337 145 40652)	74HC163D	74HC163D		week 6, 2004	84.9	6.62	1.51E8	1	1