74HC173D: Quad D-type flip-flop; positive-edge trigger; 3-state

The 74HC/1 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q0 to Q3) and master reset (MR).

When the two data enable inputs (E 1 and E 2) are LOW, the data on the Dn inputs is loaded into the register synchronously with the LOW-to-HIGH clock (CP) transition. When one or both E n inputs are HIGH one set-up time prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition.

The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH, all four flip-flops are reset (cleared) independently of any other input condition.

The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable inputs (OE 1 and OE 2) are LOW, the data in the register is presented to the Qn outputs. When one or both OE n inputs are HIGH, the outputs are forced to a high impedance OFF-state. The 3-state output buffers are completely independent of the register operation; the OE n transition does not affect the clock and reset operations.

sot109-1_3d
Data Sheets (1)
Name/DescriptionModified Date
Quad D-type flip-flop; positive-edge trigger; 3-state (REV 1.0) PDF (65.0 kB) 74HC_HCT173_CNV [English]01 Dec 1990
Application Notes (2)
Name/DescriptionModified Date
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Pin FMEA 74HC/74HCT family (REV 1.0) PDF (51.0 kB) AN11044 [English]16 Mar 2011
Users Guides (1)
Name/DescriptionModified Date
HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English]01 Nov 1997
Package Information (1)
Name/DescriptionModified Date
plastic small outline package; 16 leads; body width 3.9 mm (REV 1.0) PDF (192.0 kB) SOT109-1 [English]08 Feb 2016
Supporting Information (2)
Name/DescriptionModified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]08 Oct 2009
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74HC173DActiveHC(T)D-type flip-flops2.0 - 6.0CMOSpositive-edge trigger (3-state)+/- 7.8SOT109-11788low-40~125721.030SO1616
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74HC173DSOT109-1SO-SOJ-REFLOW SO-SOJ-WAVE
SO-SOJ-REFLOW SO-SOJ-WAVE
Reel 13" Q1/T1 CECCActive74HC173D,653 (9337 145 60653)74HC173D74HC173Dweek 12, 200584.96.621.51E811
Bulk Pack, CECCActive74HC173D,652 (9337 145 60652)74HC173D74HC173Dweek 12, 200584.96.621.51E811
Quad D-type flip-flop; positive-edge trigger; 3-state 74HCT173DB
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Pin FMEA 74HC/74HCT family 74HC_T_597_Q100
HC/T User Guide 74HCU04PW
plastic small outline package; 16 leads; body width 3.9 mm NPIC6C596A_Q100
Footprint for reflow soldering NPIC6C596A_Q100
Footprint for wave soldering NPIC6C596A_Q100
SA614A