74HC173DB: Quad D-type flip-flop; positive-edge trigger; 3-state
The 74HC/1 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q0 to Q3) and master reset (MR).
When the two data enable inputs (E
1 and E
2) are LOW, the data on the Dn inputs is loaded into the register synchronously with the LOW-to-HIGH clock (CP) transition. When one or both E
n inputs are HIGH one set-up time prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition.
The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH, all four flip-flops are reset (cleared) independently of any other input condition.
The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable inputs (OE
1 and OE
2) are LOW, the data in the register is presented to the Qn outputs. When one or both OE
n inputs are HIGH, the outputs are forced to a high impedance OFF-state. The 3-state output buffers are completely independent of the register operation; the OE
n transition does not affect the clock and reset operations.
Outline 3d SOT338-1
Data Sheets (1)
Application Notes (2)
Users Guides (1)
| Name/Description | Modified Date |
|---|
| HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English] | 01 Nov 1997 |
Package Information (1)
Supporting Information (2)
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74HC173DB | Active | HC(T) | D-type flip-flops | 2.0 - 6.0 | CMOS | positive-edge trigger (3-state) | +/- 7.8 | SOT338-1 | 17 | 88 | low | -40~125 | 148 | 42.0 | | SSOP16 | 16 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| 74HC173DB | | SOT338-1 | SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE | Reel 13" Q1/T1 | Active | 74HC173DB,118
(9351 892 50118) | HC173 | 74HC173DB |    | week 12, 2005 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
| Bulk Pack | Active | 74HC173DB,112
(9351 892 50112) | HC173 | 74HC173DB | | week 12, 2005 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
