74HC40103D: 8-bit synchronous binary down counter
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or
disabling the clock (CP), for clearing the counter to its
maximum count and for presetting the counter either
synchronously or asynchronously. In normal operation, the
counter is decremented by one count on each positive-going
transition of the clock (CP). Counting is inhibited when the
terminal enable input (TE) is
HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains
LOW for one full clock period. When the synchronous preset
enable input (PE) is LOW, data at
the jam input (P0 to P7) is clocked into the counter on the next
positive-going clock transition regardless of the state of TE. When the asynchronous
preset enable input (PL) is LOW,
data at the jam input (P0 to P7) is asynchronously forced into
the counter regardless of the state of PE, TE, or CP.
The jam inputs (P0 to P7) represent a single 8-bit binary word.
When the master reset input (MR)
is LOW, the counter is asynchronously cleared to its maximum
count (decimal 255) regardless of the state of any other input.
If all control inputs except TE
are HIGH at the time of zero count, the counters will jump to
the maximum count, giving a counting sequence of 256 clock
pulses long. Device may be cascaded using the TE input and the TC
output, in either a synchronous or ripple mode. Inputs include
clamp diodes. This enables the use of current limiting resistors
to interface inputs to voltages in excess of VCC.
sot109-1_3d
Data Sheets (1)
Application Notes (2)
Users Guides (1)
| Name/Description | Modified Date |
|---|
| HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English] | 01 Nov 1997 |
Package Information (1)
Supporting Information (2)
Ordering Information
| Product | Status | Family | Function | VCC (V) | Description | Output drive capability (mA) | Package version | Logic switching levels | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74HC40103D | Active | HC(T) | Binary counters/timers | 2.0 - 6.0 | 8-bit synchronous binary down counter | +/- 5.2 | SOT109-1 | CMOS | 15 | low | -40~125 | 56 | 1.0 | 12 | SO16 | 16 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| 74HC40103D | | SOT109-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE
SO-SOJ-REFLOW
SO-SOJ-WAVE | Reel 13" Q1/T1 CECC | Active | 74HC40103D,653
(9337 147 30653) | 74HC40103D | 74HC40103D |    | week 4, 2004 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
| Bulk Pack, CECC | Active | 74HC40103D,652
(9337 147 30652) | 74HC40103D | 74HC40103D | | week 4, 2004 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
