74HC40105D: 4-bit x 16-word FIFO register
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that
can store 16 4‑bit words. It can handle input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip‑flop, which stores a marker bit. A
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in
that position. The control flip-flop detects the state of the preceding flip-flop and
communicates its own status to the succeeding flip‑flop. When a control flip‑flop is in the
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The
clock pulse transfers data from the preceding four data latches into its own four data
latches and resets the preceding flip‑flop to logic 0. The first and last control flip-flops have
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid
data ripples through to the output end. As a result, the status of the first control flip-flop
(data‑in ready output - DIR) indicates if the FIFO is full. The status of the last flip‑flop
(data‑out ready output - DOR) indicates whether the FIFO contains data. As the earliest
data is removed from the bottom of the data stack (output end), all data entered later will
automatically ripple toward the output. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
sot109-1_3d
Data Sheets (1)
Application Notes (2)
Users Guides (1)
| Name/Description | Modified Date |
|---|
| HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English] | 01 Nov 1997 |
Package Information (1)
Supporting Information (2)
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74HC40105D | Active | HC(T) | 2.0 - 6.0 | FIFO registers | CMOS | 4-bit x 16-word FIFO register | +/- 5.2 | SOT109-1 | 15 | 30 | low | -40~125 | 67 | 1.0 | 24 | SO16 | 16 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| 74HC40105D | | SOT109-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE
SO-SOJ-REFLOW
SO-SOJ-WAVE | Reel 13" Q1/T1 CECC | Active | 74HC40105D,653
(9337 147 40653) | 74HC40105D | 74HC40105D |    | week 30, 2004 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
| Bulk Pack, CECC | Active | 74HC40105D,652
(9337 147 40652) | 74HC40105D | 74HC40105D | | week 30, 2004 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
