74HC75PW: Quad bistable transparent latch
The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are
simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When
LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs
follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD
inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in
the latches. The latched outputs remain stable as long as the LEnn is LOW. Inputs
include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of VCC.
Outline 3d SOT403-1
Data Sheets (1)
Application Notes (3)
Users Guides (1)
Name/Description | Modified Date |
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HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English] | 01 Nov 1997 |
Package Information (1)
Packing (1)
Supporting Information (1)
Ordering Information
Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Output drive capability (mA) | Package version | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74HC75PW | Active | HC(T) | 2.0 - 6.0 | Latches/registered drivers | quad bistable transparent latch | CMOS | +/- 5.2 | SOT403-1 | 11 | 4 | low | -40~125 | 111 | 1.4 | 39 | TSSOP16 | 16 |