74LV74PW: Dual D-type flip-flop with set and reset; positive-edge trigger
The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
74LV74PW: Product Block Diagram
Outline 3d SOT402-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Dual D-type flip-flop with set and reset; positive-edge trigger (REV 4.0) PDF (180.0 kB) 74LV74 [English] | 09 Dec 2015 |
Application Notes (1)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 14 leads; body width 4.4 mm (REV 1.0) PDF (285.0 kB) SOT402-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (217.0 kB) SOT402-1_118 [English] | 08 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
SPICE model
- lv Spice model (REV 1.0) ZIP LV 5/7/2013
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV74PW | Active | LV | 1.0 - 5.5 | D-type flip-flops | positive-edge trigger | TTL | SOT402-1 | +/- 12 | 11 | 75 | low | -40~125 | 124 | 2.0 | 47.9 | TSSOP14 | 14 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV74PW | | SOT402-1 | SSOP-TSSOP-VSO-WAVE | Bulk Pack | Active | 74LV74PW,112 (9351 751 40112) | LV74 | 74LV74PW |    | week 17, 2005 | 144.9 | 10.23 | 9.78E7 | 1 | 1 |
| Reel 13" Q1/T1 | Active | 74LV74PW,118 (9351 751 40118) | LV74 | 74LV74PW | | week 17, 2005 | 144.9 | 10.23 | 9.78E7 | 1 | 1 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- lv Spice model 74LV74PW
- plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LV164_Q100
- SSOP-TSSOP-VSO-WAVE LPC1114FDH28
- TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74LV164_Q100
- 74LV74
- 74LV164
