74LVC02ADB: Quad 2-input NOR gate _ BDTIC a Leading Distributor in China

74LVC02ADB: Quad 2-input NOR gate

The 74LVC02A provides four 2-input NOR gates.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

74LVC02ADB: Product Block Diagram

Outline 3d SOT337-1

Data Sheets (1)

Name/Description	Modified Date
Quad 2-input NOR gate (REV 8.0) PDF (158.0 kB) 74LVC02A [English]	15 Dec 2011

Application Notes (5)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]	04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]	05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Brochures (3)

Name/Description	Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]	10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Package Information (1)

Name/Description	Modified Date
plastic shrink small outline package; 14 leads; body width 5.3 mm (REV 1.0) PDF (295.0 kB) SOT337-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Standard product orientation 12NC ending 118 (REV 1.0) PDF (86.0 kB) SOT337-1_118 [English]	04 Apr 2013

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

lvc02a IBIS model (REV 1.0) ibs LVC02A 4/7/2013

SPICE model

lvc Spice model (REV 1.0) ZIP LVC 5/7/2013

Ordering Information

Product	Status	Family	V_CC (V)	Function	Type	Logic switching levels	Description	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74LVC02ADB	Active	LVC	1.2 - 3.6	NOR gates	NOR gates	TTL	quad 2-input NOR gate	+/- 24	SOT337-1	2.1	150	4	low	-40~125	156	40.0		SSOP14	14

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74LVC02ADB		SOT337-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74LVC02ADB,118 (9352 500 00118)	LVC02A	74LVC02ADB		week 12, 2005	123.8	3.87	2.58E8	1	1
74LVC02ADB		SOT337-1		Bulk Pack	Active	74LVC02ADB,112 (9352 500 00112)	LVC02A	74LVC02ADB		week 12, 2005	123.8	3.87	2.58E8	1	1

Quad 2-input NOR gate 74LVC02APW

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100

Pin FMEA for LVC family 74LVC1G123_Q100

Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW

Interfacing 3 Volt and 5 Volt Applications 74LVC377PW

Low voltage CMOS family - LVC 74LVC_H_245A_Q100

電圧レベルシフタ 74AVC16245DGG-Q100

Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100

lvc02a IBIS model 74LVC02APW

lvc Spice model 74LVC3G17GT

plastic shrink small outline package; 14 leads; body width 5.3 mm 74LVC32A_Q100

Footprint for reflow soldering 74HC_T_595_Q100

SSOP-TSSOP-VSO-WAVE LPC1114FDH28

Standard product orientation 12NC ending 118 74LVC32A_Q100

74LVC02A

74LV164

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