74LVC138ABQ: 3-to-8 line decoder/demultiplexer; inverting

The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected.

There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74LVC138A devices and one inverter. The 74LVC138A can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state

74LVC138ABQ: Product Block Diagram
Outline 3d SOT763-1
Data Sheets (1)
Name/DescriptionModified Date
3-to-8 line decoder/demultiplexer; inverting (REV 5.0) PDF (172.0 kB) 74LVC138A [English]19 Oct 2011
Application Notes (5)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x... (REV 1.1) PDF (191.0 kB) SOT763-1 [English]30 May 2016
Packing (1)
Name/DescriptionModified Date
DHVQFN16; Reel pack, SMD, 7" Q1/T1 standard product orientation Orderable part number ending ,115 or... (REV 2.0) PDF (191.0 kB) SOT763-1_115 [English]05 Jul 2016
IBIS Model
SPICE model
Ordering Information
ProductStatusFamilyFunctionVCC (V)DescriptionLogic switching levelsPackage versionOutput drive capability (mA)tpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC138ABQActiveLVCDecoders/demultiplexers1.2 - 3.6invertingCMOS/LVTTLSOT763-1+/- 242.7low-40~1259414.563DHVQFN1616
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVC138ABQSOT763-1Reel 7" Q1/T1Active74LVC138ABQ,115 (9352 733 34115)VC138A74LVC138ABQAlways Pb-free123.83.872.58E811
3-to-8 line decoder/demultiplexer; inverting 74LVC138APW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvc138a IBIS model 74LVC138APW
lvc Spice model 74LVC3G17GT
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x... NPIC6C596A_Q100
DHVQFN16; Reel pack, SMD, 7" Q1/T1 standard product orientation Orderable part number ending ,115 or... NPIC6C596A_Q100
74LVC138A
TFF1024HN