74LVC1G00GX: Single 2-input NAND-gate
The 74LVC1G00 provides the single 2-input NAND function.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
sot1226_3d
Data Sheets (1)
Application Notes (3)
Package Information (1)
Packing (1)
Supporting Information (1)
| Name/Description | Modified Date |
|---|
| MAR_SOT1226 Topmark (REV 1.0) PDF (35.0 kB) MAR_SOT1226 [English] | 03 Jun 2013 |
IBIS Model
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Type | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74LVC1G00GX | Active | LVC | NAND gates | 1.65 - 5.5 | CMOS/LVTTL | single 2-input NAND gate | NAND gates | +/- 32 | SOT1226 | 2.2 | 175 | 1 | low | -40~125 | 327 | 94.5 | 195 | X2SON5 | 5 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| 74LVC1G00GX | | SOT1226 | | Reel 7" Q3/T4, Reverse | Active | 74LVC1G00GX,125
(9352 983 74125) | VA | 74LVC1G00GX |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
