74LVC1G07GN: Buffer with open-drain output

The 74LVC1G07 provides the non-inverting buffer.

The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Outline 3d SOT1115
Data Sheets (1)
Name/DescriptionModified Date
Buffer with open-drain output (REV 11.0) PDF (349.0 kB) 74LVC1G07 [English]29 Jun 2012
Application Notes (4)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]30 Dec 2010
Package Information (1)
Name/DescriptionModified Date
extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English]04 Apr 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionOutput drive capability (mA)Package versionfmax (MHz)No of bitsPower dissipation considerationstpd (ns)Tamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC1G07GNActiveLVCBuffers/inverters/drivers1.65 - 5.5CMOS/LVTTLopen-drain32SOT11151751low2.2-40~12535827.3222XSON66
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVC1G07GNSOT1115Reel 7" Q1/T1, Q3/T4Active74LVC1G07GN,132 (9352 917 73132)VS74LVC1G07GNAlways Pb-free123.83.872.58E811
Buffer with open-drain output 74LVC1G07GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
MicroPak soldering information NTS0102_Q100
MAR_SOT1115 Topmark 74AUP1G332
74LVC1G07 IBIS model 74LVC1G07GX
SOT1115 74AUP1G332
Reel 7" Q1/T1, Q3/T4 74AUP1G332
74LVC2G17