74LVC1G10GS: Single 3-input NAND gate
The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
sot1202_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Single 3-input NAND gate (REV 4.0) PDF (155.0 kB) 74LVC1G10 [English] | 10 Sep 2014 |
Application Notes (4)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
| MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English] | 30 Dec 2010 |
Brochures (1)
| Name/Description | Modified Date |
|---|---|
| Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English] | 10 Jul 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm (REV 1.0) PDF (192.0 kB) SOT1202 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1202_132 [English] | 04 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1202 Topmark (REV 1.0) PDF (49.0 kB) MAR_SOT1202 [English] | 03 Jun 2013 |
IBIS Model
- 74LVC1G10 IBIS model (REV 1.0) ibs LVC1G10 10/21/2014
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Type | Logic switching levels | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G10GS | Active | LVC | 1.65 - 5.5 | NAND gates | single 3-input NAND gate | NAND gates | CMOS/LVTTL | SOT1202 | +/- 32 | 2.6 | 175 | 1 | low | -40~125 | 336 | 33.0 | 226 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G10GS | | SOT1202 | Reel 7" Q1/T1, Q3/T4 | Active | 74LVC1G10GS,132 (9352 928 98132) | YM | 74LVC1G10GS |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Single 3-input NAND gate 74LVC1G10GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Pin FMEA for LVC family 74LVC1G123_Q100
- MicroPak soldering information NTS0102_Q100
- Low voltage CMOS family - LVC 74LVC_H_245A_Q100
- MAR_SOT1202 Topmark NCX2200GS
- 74LVC1G10 IBIS model 74LVC1G10GW
- XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm NCX2200GS
- Reversed product orientation 12NC ending 132 NTS0101
- 74LVC2G17
