74LVC1G125GN: Bus buffer/line driver; 3-state
The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH-level at pin OE causes the output to assume a high-impedance OFF-state.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Outline 3d SOT1115
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Bus buffer/line driver; 3-state (REV 11.0) PDF (364.0 kB) 74LVC1G125 [English] | 02 Jul 2012 |
Application Notes (4)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
| MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English] | 30 Dec 2010 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English] | 04 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English] | 03 Jun 2013 |
IBIS Model
- 74LVC1G125 IBIS model (REV 1.2) ibs LVC1G125 10/21/2014
Ordering Information
| Product | Status | Family | Function | VCC (V) | Description | Logic switching levels | Output drive capability (mA) | Package version | fmax (MHz) | No of bits | Power dissipation considerations | tpd (ns) | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G125GN | Active | LVC | Buffers/inverters/drivers | 1.65 - 5.5 | single buffer/line driver (3-state) | CMOS/LVTTL | +/- 32 | SOT1115 | 175 | 1 | low | 2.1 | -40~125 | 338 | 23.5 | 210 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G125GN | | SOT1115 | Reel 7" Q1/T1, Q3/T4 | Active | 74LVC1G125GN,132 (9352 902 41132) | VM | 74LVC1G125GN |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Bus buffer/line driver; 3-state 74LVC1G125GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Pin FMEA for LVC family 74LVC1G123_Q100
- MicroPak soldering information NTS0102_Q100
- MAR_SOT1115 Topmark 74AUP1G332
- 74LVC1G125 IBIS model 74LVC1G125GW
- SOT1115 74AUP1G332
- Reel 7" Q1/T1, Q3/T4 74AUP1G332
- 74LVC2G17
