74LVC1G126GF: Bus buffer/line driver; 3-state
The 74LVC1G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A LOW-level at pin OE causes the output to assume a high-impedance OFF-state.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74LVC1G126GF: Product Block Diagram
![74LVC1G126GF: Product Block Diagram](/image/nxp/mna125.gif)
Outline 3d SOT891
![Outline 3d SOT891](/image/nxp/sot891_3d.gif)
Data Sheets (1)
Application Notes (5)
Brochures (1)
Package Information (1)
Packing (1)
Supporting Information (2)
IBIS Model
Ordering Information
Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Package version | Output drive capability (mA) | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74LVC1G126GF | Active | LVC | Buffers/inverters/drivers | 1.65 - 5.5 | CMOS/LVTTL | single buffer/line driver (3-state) | SOT891 | +/- 32 | 175 | 1 | 2 | low | -40~125 | 313 | 7.8 | 158 | XSON6 | 6 |