74LVC1G126GV: Bus buffer/line driver; 3-state
The 74LVC1G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A LOW-level at pin OE causes the output to assume a high-impedance OFF-state.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74LVC1G126GV: Product Block Diagram
Outline 3d SOT753
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Bus buffer/line driver; 3-state (REV 12.0) PDF (363.0 kB) 74LVC1G126 [English] | 02 Jul 2012 |
Application Notes (5)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
| MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English] | 30 Dec 2010 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic surface-mounted package; 5 leads (REV 1.0) PDF (243.0 kB) SOT753 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (186.0 kB) SOT753_125 [English] | 29 Nov 2012 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT753 Topmark (REV 1.0) PDF (89.0 kB) MAR_SOT753 [English] | 03 Jun 2013 |
IBIS Model
- 74LVC1G126 IBIS model (REV 1.1) ibs LVC1G126 10/21/2014
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G126GV | Active | LVC | Buffers/inverters/drivers | 1.65 - 5.5 | CMOS/LVTTL | TTL enabled (3-state) | +/- 32 | SOT753 | 175 | 1 | 2 | low | -40~125 | 270 | 63.3 | 169 | TSOP5 | 5 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G126GV | | SOT753 | Reel 7" Q3/T4, Reverse | Active | 74LVC1G126GV,125 (9352 718 88125) | V26 | 74LVC1G126GV |    | week 36, 2003 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Bus buffer/line driver; 3-state 74LVC1G126GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Pin FMEA for LVC family 74LVC1G123_Q100
- MicroPak soldering information NTS0102_Q100
- PicoGate Logic footprints NX3L4684
- MAR_SOT753 Topmark 74LVC1G17_Q100
- 74LVC1G126 IBIS model 74LVC1G126GW
- plastic surface-mounted package; 5 leads 74LVC1G17_Q100
- Tape reel SMD; reversed product orientation 12NC ending 125 74LVC1G17_Q100
- 74LVC1G126
- BAP70Q
