74LVC1G80GX: Single D-type flip-flop; positive-edge trigger
The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
sot1226_3d
Data Sheets (1)
Application Notes (3)
Package Information (1)
Packing (1)
Supporting Information (1)
| Name/Description | Modified Date |
|---|
| MAR_SOT1226 Topmark (REV 1.0) PDF (35.0 kB) MAR_SOT1226 [English] | 03 Jun 2013 |
IBIS Model
SPICE model
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74LVC1G80GX | Active | LVC | D-type flip-flops | 1.65 - 5.5 | CMOS/LVTTL | positive-edge trigger | SOT1226 | +/- 32 | 2.4 | 450 | low | -40~125 | 327 | 94.5 | 195 | X2SON5 | 5 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| 74LVC1G80GX | | SOT1226 | | Reel 7" Q3/T4, Reverse | Active | 74LVC1G80GX,125
(9352 983 84125) | VT | 74LVC1G80GX |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
