74LVC2G00GX: Dual 2-input NAND gate
The 74LVC2G00 provides a 2-input NAND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Data Sheets (1)
Package Information (1)
Packing (1)
Ordering Information
| Product | Status | Family | VCC (V) | Logic switching levels | Type | Output drive capability (mA) | Description | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74LVC2G00GX | Introduction Pending | LVC | 1.65 - 5.5 | CMOS/LVTTL | NAND gates | +/- 32 | dual 2-input NAND gate | 2.2 | 175 | 2 | low | -40~125 | | | | X2SON8 | 8 | SOT1233 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF |
|---|
| 74LVC2G00GX |  | SOT1233 | | Reel 7" Q1/T1 | Development | 74LVC2G00GXX
(9353 084 44115) | Standard Marking | | |
