74LVC2G17GN: Dual non-inverting Schmitt trigger with 5 V tolerant input
The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Outline 3d SOT1115
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Dual non-inverting Schmitt trigger with 5 V tolerant input (REV 8.0) PDF (200.0 kB) 74LVC2G17 [English] | 02 May 2013 |
Application Notes (3)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English] | 04 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English] | 03 Jun 2013 |
IBIS Model
- 74LVC2G17 IBIS model (REV 1.0) ibs LVC2G17 10/21/2014
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G17GN | Active | LVC | 1.65 - 5.5 | Schmitt-triggers | CMOS/LVTTL | dual buffer Schmitt-trigger | +/- 32 | SOT1115 | 3.6 | 175 | 2 | low | -40~125 | 274 | 11.6 | 170 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G17GN | | SOT1115 | Reel 7" Q1/T1, Q3/T4 | Active | 74LVC2G17GN,132 (9352 918 03132) | Standard Marking | 74LVC2G17GN |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Pin FMEA for LVC family 74LVC1G123_Q100
- MAR_SOT1115 Topmark 74AUP1G332
- 74LVC2G17 IBIS model 74LVC2G17GW
- SOT1115 74AUP1G332
- Reel 7" Q1/T1, Q3/T4 74AUP1G332
- 74LVC2G17
